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Recent content by I_THINK_ITS_SHORTED

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    Altera Cyclone IV FPGA SPI

    I'm not sure what the correlation is but in my test code I am using "alt_avalon_spi_command" for general read and write from the SPI. I changed the flag value parameter in the function to "ALT_AVALON_SPI_COMMAND_MERGE" and this fixed the problem of the MISO signal mimicking the MOSI. The...
  2. I

    Altera Cyclone IV FPGA SPI

    I double checked the wire connections and they are all correct.
  3. I

    Altera Cyclone IV FPGA SPI

    I monitored the lines using signaltap and the result makes me think the SPI 3-wire controller can only be used for 3-wire SPI and not 4. Basically MOSI and MISO both go high simultaneously during a byte transfer. The SRAM I'm using requires separate in and out lines, not one bidirectional...
  4. I

    Altera Cyclone IV FPGA SPI

    I'm having some trouble getting serial SRAM to work using the Altera DE2-115. I tried using the "SPI (3 Wire Serial)" IP core, but after mapping the exported signals to the GPIO pins I can't seem to properly control the memory. I'm also not sure if its a problem that the SRAM is 4 wire SPI...
  5. I

    [SOLVED] How to disable refresh on the Altera DE2-115 SDRAM

    This is the info I needed. I'll look into the refresh logic in the Verilog file and see what modifications I need to make to prevent refreshing. I also found the datasheet for the sdram, which includes truth tables showing which signal combinations correspond to the refresh functions. Between...
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    [SOLVED] How to disable refresh on the Altera DE2-115 SDRAM

    I'm working on a project and I need to completely disable the refresh of the Altera DE2-115 SDRAM, which would allow me to measure retention time of the SDRAM cells. So far I have tried modifying the SDRAM_REFRESH_PERIOD in Qsys under the SDRAM timing settings. I tried setting it to 0, and I...
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