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When I use Ap0lll0 to Design my Circuit , I meet These questions:
Timing graph cleared.
#(xdb_copy.c: 1078) Net VDD with no sink (1 times)
#(xdb_misc.c: 644) xdb_fill_port_position() port 'div' no pin found (7 times)
DRC Brief Error Summary
Error Type Num Description
Met1 Spacing 100 metal1...
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