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Recent content by hrushitha

  1. H

    routing variations - timing and routing, scaling factor

    routing variations how encounter tool will do the timing and routing if i change scaling factors from (cap)1 to 1.8 and 1 to 1.6(res). how will be the routing if scaling factor is 1 and how it changes from 1.8. what is the difference between them thanks
  2. H

    need of hold check for a flip flop??

    what is the need of a hold check for a flip flop? thanks
  3. H

    slew propagation in cdb.

    we have slew info in .lib,but what is the special in the .cdb slew propagation. how it differs from .lib slew. i mean cdb contains propagated slew and arc current models. my question is how make cdb generates this propagated slew. i think now u can understand the purpose of my question thanks
  4. H

    slew propagation in cdb.

    hi all please help me, thanks
  5. H

    How power switches and decoupling capacitances are optimized with power rail analysis

    hi all, How Power switches and de-coupling capacitances are optimized using power rail analysis.what is the relation between these. thanks
  6. H

    65 nm Leakage Problem

    hi all, discussions were good. can anyone elaborate this "More importantly, the leakage (static) is dependent on the VGS on the gate and also the area of the device. So, design with a smaller area and a smaller VGS. In case you are using a transistor which takes logic 1 and logic 0, then use a...
  7. H

    what is the difference between .cdb and UDN

    hi all what is the difference between UDN(user defined noise) models and .cdb by make_cdb models. can any one tell me what exactly they consists. thanks
  8. H

    What are the channel-connected component (CCC) inputs?

    hi what is channel-connected component (CCC) inputs. thanks.
  9. H

    slew propagation in cdb.

    hi all, how cdb creates the characterization table for slew propagation. thanks
  10. H

    What is the clock gating setup and how does it affect timing?

    Re: clockgating thanks alot friends
  11. H

    how a tool calculates the cap and resistance values?

    extended cap table hi all what is there inside extended cap table (i mean how tool calculates the cap and resistance values) coyote field solver gives the table for extended cap table in that what are the columns represented for??? i know for basic cap table (width space total capacitance...
  12. H

    Interconnect in High speed circuits??

    can anyone reply to the above question??
  13. H

    What is the graybox view from gds2 ?

    gdsii what is graybox view from gds2. if i give gds2 to libgen which information it takes from gds2. thanks
  14. H

    Can anyone please explain the syntax of SPEF?

    spef syntax *p hello ac123, i am also analyzing the same thing except instance name i don't understand anything in SPEF. if u have any good stuff please let me know thanku
  15. H

    Which companies fabricate ASIC based on your design files?

    Re: fabrication of ASIC hi, a single chip can't fabricate,becoze it is very costly,number of chips make on a single wafer.wafer cost also increases day by day with technology. regards
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