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Hello everyone
I'm trying to use smoke analysis with imported MOS model, it works well with spice but the smoke only provides me the PDM paramater but impossible to have VGS, ID etc... a red flag indicates me "Current data not found for SMoke test ID". I have already set ALL to Voltage...
Hello again,
I have another problem :
the compilation of my project seem to work fine but when I try to debug, there is something wrong with "assert" function (linker error), does someone know which file I need to define this function ?
thanks for your help
Hello,
I'm beginning a blank project with IAR environment and would want to know what is the file I have to add in my project to recognize "uint8_t" "uint32_t"... type ?
Examples in the Discovery use this kind of type but I can't find the stdint.h or another file that describe this type...
Hello
I'm looking for a book which could explain the small signal analysis of oscillator (Colpitts, Clapp...)
The only book I found present oscillator in RF domain... I don't use it in this freq range (a 100Khz to 10MHz)
Do you know a course / ebook / book which could help me ?
Thanks for your...
Hello all,
I'm looking for a reference book or any guideline in order to estimate the Equivalent Noise Bandwidth of a low pass bessel filter (4th order).
Do you know a book that could help me to evaluate it ?
regards
Hello
I would want to evaluate the value of R2 and Vref in order to have an hysteresis voltage of 0.1V and a threshold- of 2.45V.
here is the schematic :
So I apply
VH=R1/(R1+R2)*Vsat+
And
VTH-=R2/(R1+R2)*VREF
Because VSAT-=0V.
Fo the reference voltage I have 2.485V and for...
Hello all,
Thanks for your replies... FvM, I don't use DCO since I would want to minimize the line beetwen the analog board (with ADC) and the digital board (which receive only DATA form my 8 ADCs), so I don't need the DCO which is the echoed clock from ADC.
What is a FF controller ?
If I...
Hello TrickyDicky
First, thanks for your reply ;
Since I have 8 ADC, do I must have 8*2 PLL to synchronize the reception ? or since the CLK is the same (without considering PCB tracks delays)
can I imagine only 2 PLL :
the CLK signal (which is the Clock of the ADC)
the CLK2 signal (ADC clock...
Hello,
Thanks for you help.
If I understand well, I have to generate the three clocks signal with 120° of difference of phase.
Then, for each process, the DATA is captured, and another process analysis the result of each captured signal and try to identify the "010" header to know which is the...
Hello,
I need help to design a receiver :
I use a AD7626 ADC in "self-Clocked mode" (page 23 in datasheet : https://www.analog.com/static/imported-files/data_sheets/AD7626.pdf )
In this mode, the clock is not present, the data contain an header '010' which permit to the receiver to recover the...
In this case, what does the voltage source represent ? is it just to have a voltage reference to deduce the noise contribution of the stage ? what is the voltage value could you suggest me ?
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