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Just I want to know what's the suitable layer to draw the "No conductive trace" region? And if there is a configuration in Alitum to avoid routing in this region when I will use the auto-routing option
Hello,
While I'm designing a footprint of a sd-card component I found in the datasheet some regions written on it "No Conductive traces". Is this mean that I haven't to route any trace in this region? I'm using Altium, so what's the suitable layer for darwing these regions: Mechanical layer...
Hi,
I have designed a board and I made an error when I calculated my thru-hole diodes footprint. In fact the recommended footprint of the hole is 1 mm, but my footprint hole is equal to 0.7 mm. Can any one give me a reference of a diode which has a pin dimension less than 0.4mm ? Or can someone...
Hello,
When I make a multilayer board with planes, I see a green zone in the edges of my Board which is the pullback zone.
can I route traces or add pads in this green zone?
Also, I'm using a model board for my design. In this model board the trace width is 0.2mm, clearance is 0.2 mm and pads...
Hello,
I'm designing a Zigbee module with a TI antenna design.
I make the Antenna with the fill copper option of AD10. Well, when I added a two pads to the fill copper of the antenna I found two errors violations:
1- Clearance Constraint (Collision < 0.2 mm) Between Fill on BottomLayer And...
Hello,
I'm designing a test board. I need to have a small keyboard which has 6 keys. I make a long search on the internet without result.
can any one give me a datasheet of a small keyboard which has 6 or 9 keys.
Thanks,
I have connected this net "DVDD_3V" only in the top and bottom layer, for the other pins this pins it's connected properly, so I'm wodering why it's not the same case of this 2 pins montioned in the image?
For the power plane, before this power plane was assigned to 1.8v net but when I splited...
Well,
First, I noticed that there are no clearance between the power plane and different net, what I have to do?
See image1:
Also, It stills 5 vioalation rules at my PCB design, I will show just one viaolation rule and could you tell me what's the problem (It's the first time that I make...
Well, I changed the clearance value of plane from 0.508 mm to 0.1mm also I changed the connect style from relief connect to direct connect, the number of violation rules decreased from 500 to 5. But I don't know if my board will work with a clearance value equal to 0.1 mm, also what's better to...
Sorry, I didn't understand you, well the clearance I have 2 rules: rule 1 is between (trace ,via and pads) is 0.1 mm.
The second is petween polygon pours and (trace,via pads) is 0.1 mm.
This is an image example of my board (the bright green color is the rule violation) :
Regards,
Hello,
I have a 38mmx38mm PCB, my stack-up layer is like this: TOP/GND1/SIG1/SIG2/GND2/SIG3/PWR1/BOT.
I finished routing my board, now I try to make the partition of Power and GND. (It's the first time that I make a multilayer PCB)
I have 2 GND planes connected to GND net and I have 1 power...
Well, it's the first time that I make a multilayer board, when I finished the board,Altium inform me that I have many dead copper in my board (unrouted GND&Power nets)
Knowing that I'm working with 3 power levels and with high frequency conditions.
Hello,
Yesterday,I finished routing my board with this layer stackup:
TOP/GND1/SIG1/SIG2/GND2/SIG3/PWR1/BOT.
Some people told me that this stuckup is assymmetrical and may be my board didn't work, others told me that they used this stuckup before and their boards work fine.
I need to know...
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