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Hi thanhFF,
Check set pindata variable. U will find various options for it. The three bits which you are referring depends on this command. The three bits refer to preclock, clock and postclock data. U can find this information in the tetramax document.
Hi Jeevan,
I resolved that Warning. But still i am not able to get the clocks those are in .libs to my current design. Do i need to redclare them again? How i can make those clocks available to my design.
Hi all,
I am using pt for STA. In my design there is one Analog phy, i was provided an .lib file of the hard macro. During my sta i read that file using read_lib.
But the clocks that were in the phy are not available to my current design.
Do I need to redefine that phy clocks in my...
Hi all,
When do we define generated clocks? Do we need to define the pll outputs as generated clocks during synthesis.I am using design compiler for synthesis.
Some one help me plz.
Hi ljxpjpjljx,
In my .lib there are RECREM related items, where i need to check the hierarchy, the tool will map the library to the sdf by using library cell name right?
Hi all,
I am doing sdf simulations with ncsim. I enabled negative timing checks and specified RECREM and NTC options. But the tool is reporting warning as non exisitng timing checks for all the RECREM consructs, but actually in my lib file i have recrem related information, i was...
Hi shobhit,
What are the tools you are using for scan insertion.Can you provide some information of On-chip-controller block like how u r providing the high frequency clock, tool inserted or manually inserted OCC...
Tetramax is synopsys tool for ATPG. U require any one of the below tools to run ATPG.
Synopsys Tetramax
Mentor Testkompress.
I dont remember the name ot the tool but there is some tool from cadence also
Hi poluekt,
can you please elaborate it. what happens if we define the signals both as spec and existing_dft.
when do we use -type Testdata? Can you plz clear these
I am working for testchips. We dont have any information about the top level design with which my testchip is going to integrate. Please suggest me what will be the better approach.
What is the better way to set input_transition?Is it the way to select a buffer as driving cell on all inputs or explicitly specifying the value by using set_input_transition command. If we want to specify the value how we need to calculate this value.
Run ATPG, as these are pre dft violations that occurs before inserting scan the tool can fix most of these warnings during scan stiching if your setup is properly done.
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