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Recent content by holddreams

  1. H

    Can anyone introduce some analog ic design compancies in Canada?

    Are there many analog ic design companies in Canada? Can anyone give some links? Is it easy to find a job for analog ic design engineer in Canada? Thanks!
  2. H

    (W/L) ratios from specifications of analog circuits

    You can search for the project solutions of EECS240, which gives the design flow for different types of differential OTAs. Also EE214 lecture give an example of differential OTA design using gm/id methodology.
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    Help with gmro vs. VDS curve

    Hi, In ee214 lecture, ft=1/(2*pi)*gm/Cgg, where Cgg=Cgs+Cgd+Cgb. You can search ee214 lecture to review it. Best Regards, Xianguang
  4. H

    If you need help with ESD... ask me in this post

    Hi, If PMOS driver uses ballast resistor, how to realize? With pwell res? If there is no Pwell for the process, how should we do?
  5. H

    Help with gmro vs. VDS curve

    In the attachment, page 7, answer d, there is gmro vs vds curve, which is just like the waveform you pasted. With spectre simulator, I can measure ro=1/gds, gm respectively. I do not know wheter pspice can do it or not. You can also refer ee214 lecture which give some spice netlist for...
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    OTA sizing by gmoverid approach

    I use Cadence composer to draw schematic, Virtuoso to draw layout, spectre and spectremdl to run simulation. Change the testbench in EE214 to spectre format, record the gmoverid, ids, etc ,and can easily get the waveform just like in the paper. 1)Edit "gmid_nmos_ee214.scs" //NMOS gm/id...
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    OTA sizing by gmoverid approach

    Hi, EmbdASIC, In EE214, gm/id simulation test bench is in the attachment. Also, in EECS240, gm/id simulation test up is using a diode connected NMOS and sweeping the Vds. You can try both. Best Regards
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    [help]Design issues on two stage foled cascode OTA

    Hi DenisMark, Have you ever simulated open-loop gain vs vod, AC loop gain @Vod=0 and AC loop gain @vod=vod,max which were described in EE240 project? How to add the stimulus? Best Regards.
  9. H

    How to get the inl/dnl of current-steering DAC?

    How to simulate the inl/dnl of current-steering DAC? How to get the waveform just like in the attachment? Thanks.
  10. H

    Question about the plot for gm/Id methodology

    v*=vgs-vt, usually use v*=200mv for design. vth≠vth0 Just my points.
  11. H

    How to download EE214 video?

    att.
  12. H

    asking for spice netlist for berkeley ee240

    Which circuit do you want to simulate? And what is your simulation tool? Hspice or Spectre?
  13. H

    ic610 in ubuntu8.04 error

    Before adding these issuses, I can start icfb& and draw the schematic,etc even if the two errors are still existing.

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