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i am working on a sigma delta adc second order three bit and i do the schematic design on cadence and i get 100 db and it is ok when i make the layout and make post layout it become 93db i found in the drawing of fft a pulse at another frequency 200hz(my input frequency is 100hz and band width...
when i simulate a sigma delta adc in cadence a time it is perfect another time it got bad and it is the same circuit does any one say to me why?????????????????????????????????????????????????????
i had been design a second order 3-bit sigma delta adc with osr=128 fs=50KHZ and band width of input frequency is 200hz and resolution is 14bit when i run the simulink design i got 99 db but when i run on cadence it become 60db i expect it is from the sampes i take from the cadence to matlab can...
when i want to calculate the SNR of output of sigma delta i run the design on cadence for 6 sec(as i have input=100hz &sampling frequency =50Khz)
and i take it on matlab to calcsnr when i take samples very close from end the snr become 97db but when i go to the middle it become 60db so how many...
first:
i want to put a dc input on a switched capacitor integrator how can i do this
second i make a sigma delta modulator and iwant to put the dac in the integrator and make the feed back bits to control the switches how can i do this
please i want any one to replay to me
hi all
i am working on a sigma delta modulator using .13um technology and i want an output from the DAC ranging from .225 to 1.575 and my Vdd=1.8 so i can't do that as my common mode input is .9 how can i do this big swing DAC
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