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Re: comparator design
can u upload the transient simulation results and schematic?this will help us understand better.
are the oscillations only during the h-l transition? this problem can occur if pmos is made strong enuf that input cant override the data at the output....
I am using the 1.5bits per stage architecture and hence the gain in each stage would be 2.
Added after 3 minutes:
this paper is usefull papar about comparator...
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