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hi cyrax747,
1/ DEF file
2/ I think you will need cell/macro information (from LEF) for linking your design.
3/ RC corner
that's what I am using to extract.
hi Raj1435,
it's not from what you "constraint" the path (in your design). it come from what you designed
- your launch flop L : normal, CK feed clock pin of your flop
- your capture flop C : the CK signal is inverted to original.
--> you launch data from L at rising edge of clock pin L, and...
hi yuhiub90,
as I mention, uncertainty is margin/budget timing for your design, it models skew,jitter,... timing tool will make report more pessimism by uncertainty. and this is what we need to safe design. you can't make sure 100% that the skew is the same at any time, any where, as your chip...
hi Yuhiub90,
as I'm using uncertainty in synthesizing, it's just used as a margin which you want to reserve for Back-End later.
in my case, synthesizer do not build clock tree follow the uncertainty and clock-tree timing is idea.
I put a short report timing to you bellow:
Point...
hi raj,
I'm not an expert on it, but I have somethings to share.
- trans violations might come from big load as the previous pin drive.
- to fix it, I think you need to use a stronger cell (of course you have to trade off timing/power/...) or break number of fanout (to reduce load)
as I know...
hi gstekboy,
I need to be cleared about your input database to PT: your netlist and SDF are exported from DC, aren't it ?
if yes, when you read them into PT, it just annotate SDF to netlist (what is DC already calculated) --> should be the same - I think.
to see difference, I think you should...
hi friend,
I think - input pin capacitance is used for calculating capacitance of net which connect to the cell in design. total net cap = output cap of pin + net alone cap + cap at input pins which the net connect to.
I often see in library that the cap of an input pin is 0. (maybe due to...
why do you care about asynchronous paths?
in STA, you have to specify asynchronous domains as they're (set_clock_group async), and the tool will consider them as false paths together. if you do not specify, then STA tool consider them like sync domains and check timing between them by searching...
1. in case, have no real path between clk1_in and clk2_in
set_clock_groups -logically_exclusive -group {clk1_in} -group {clk2_in}
2. you mean: create_clock clk1_in and generated_clock clk2_in source from clk1_in -div 4 , is that ?
--> still need to set_clock_group if have no read path between...
hi friend,
if you run your design 100x , I wonder 2 things here:
1. did you check resolution of simulation ? if your period lower than the resolution, so the simulation might not perform correctly
2. your design is close with normal freq, if you pick up it to 100x freq, surely your design will...
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