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Recent content by hltong

  1. H

    spectre using hspice netlist

    You should add +spp option when simulation .
  2. H

    How to make pins outside the cell in Virtuoso Layout Editor?

    Layout question When you make a cell . the connective of layoutxl is miss . you should create pin in the make cell .
  3. H

    capacitor mismatch analysis

    Here is a sample . 10Bit 100M ADC . MC cap mismatch is 0.3%
  4. H

    What is the best layout editor?

    I think Laker is better than virtuoso . when layout standcell , Laker is easy to deal whith .
  5. H

    About Ultrasim Post-Layout simulation

    Can some body give me some docs/stuff related to PLL Post-Layout simulation . simulation tools is cadence ultrasim . I have extracted the R & C dspf , But I cannt simulation use it .
  6. H

    High load output capacitance in LVDS and CML output buffers

    LVDS and CML Hi I am layout a LVDS . But dont the key point . Who can give me some help ??
  7. H

    Virtuoso XL Layout editor,who can help me,thankyou!

    You can ask cadence provided the training material and the database . I think cadence will help you .
  8. H

    how to create .io file for layout

    how to create io file encounter Yes . You can place IO Cell randrom . then write the file ioplace.ioc and manual edit it . reload the file . It will OK.
  9. H

    problem of running IC5141 in Suse 9.3

    ipcisaliveprocess connection timeout You can get the answer on sourcelink.cadence.com
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