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Recent content by hkrist

  1. H

    Nanosim integration with VCS

    Hi all, I have some problem when I use the ns_vcs tool. Q1. I am able to simulate the whole chip including digital and analog part, so I think the flow is correct. There is a spice mode of SRAM in my design, it takes a lot of time to simulate. I want to accelerate the simulation by using...
  2. H

    Mincut violations in Encounter

    Thank you for your answers. I found it is reported only in VIA4 by encounter, but when I run DRC in Calibre there are errors in other vias.(i.e. VIA1, VIA2, VIA3) Finally I fixed the problem with shobhit's method by using Laker. - - - Updated - - - I fixed the problem in Laker, but I want to...
  3. H

    Whether metal filler over macros or not in Encounter

    Hi all, If I add the metal filler in the region of core whether the metal filler are added on the top of macros(e.g. sram or other analog circuits). I have asked my friend, he said the metal filler would be added all over the region. But it was added all the region except the top of macros, I...
  4. H

    Mincut violations in Encounter

    Hi all, I got some violations in Encounter after finished nanoroute. The violations in browser are the type of mincut. How can I resolve them? Please give me some help.
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    CTS problem in SOC Encounter

    pin connection problem in encounter Hi all, In the previous post, I found there is no connection at the pin of clock pad and the CLK of sram macro after CTS. I think it just happened in clock pins after CTS. However, today I skip the problem and finish doing nanoroute. Besides clock pins, the...
  6. H

    CTS problem in SOC Encounter

    Hi all, I met a problem when I used SOCE to implement my design. After the step of CTS, I found the clock tree didn't connect to the pin of clock input pad and the pin of CLK of SRAM macro. I read the log of encounter and found there were some warnings. I think maybe the warnings are the...
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