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Hello again everyone,
I changed my simulation a bit and I have tried to incorporate all the fixes that are recommended here.
Here is my simulation:
and the output:
If you noticed, the output is obtained between the bi-directional and the half bridge MOSFETs.
If I try to simulate the circuit...
So I have to use a 12V regulator and make a veroboard that would provide power to all gate drives and then use opto-coupler in between them, please refer to the image:
Ignore the multiple drives and couplers (just want to confirm if the circuit is correct).
Yes that is what we require and isn't the configuration in the third image more like a half-bridge configuration.
As far as the tailoring is concerned, I have tried caps and inductors of different values in my previous config. I will try to implement the configs that you have provided and hope...
Guys, I am getting desperate and I have tried every method provided and I am not getting any results.
I am getting short on time as I will have to present the project's progress to my supervisors before the end of this month and I am not confident that such progress, until now, will be...
Even if I increase the capacitance of C1 and C2 upto 1000uF, the output remains the same.
Do you mean I have to increase the frequency of the gating signals or do you mean something else?
I tried to simulate your circuit on PSpice, please see your model:
and the output of the simulation:
I also tried using MOSFETs to do the job but the result was not plausible. I also tried to accomplish the same task with JFETs and "somewhat" got "some" result.
I am not sure what mistake I...
So I have to use three opto-couplers with the gate drivers having the same power source and I should use a single arduino for the waveform synchronization, would that solve the isolation problem?
Are you talking about the schematic in post#8 (maybe partially), it would be helpful if you could...
The figure below depicts the basic concept (as far as the hardware is concerned):
Does that "Isolate" the gate drives? Please do correct me if I am wrong.
The goal is to design an inverter and obtain a "Modified Sine Wave" as given in post #6.
I used different laptops to power the arduinos...
Thank you for the reply.
Yes you are right but apparently if I do not apply the bottom ground of the C2 cap then this is the output:
I had to attach this ground in order to get some viable output.
Moreover, this circuit is not supposed to give to low VAC but apparently it does (which is...
The circuit of the BSNPC inverter along with the gate drives is:
and its corresponding output:
I cant seem to be getting the negative half pulses of the modified sine wave.
Also I want to ask, would it matter if the bidirectional switch is designed by using P-channel MOSFETs and the half...
Can you recommend any counter ICs in PSpice ?
@KlausST yes, you are absolutely correct but to be honest there isn't anything mentioned like that at all in the research paper that we are trying to study and are trying to obtain the similar results as that of the paper.
Here is the complete...
First of all, thank you for taking the taking the time to reply.
Secondly, yes they are inverses of each other but not quite exactly the case because if you notice, the off-time of the first signal is more than the on-time of the second signal (that is after T/2).
Hello,
I am a newbie in PSpice and I want to know from you professionals that, is it possible to implement the signals given in the below figure?
Kindly guide me. Any comment will be highly appreciated.
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