Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
There is a sigma-delta pll. When the divide ratio is integer and sdm (with dither) is on, the tested phase noise profile is fluctuating largely. But when the divide ratio is fractional, the fluctuation is very small. What's the reason?
Hi all,
There is a sigma-delta pll. When the divide ratio is integer and sdm (with dither) is on, the tested phase noise profile is fluctuating largely. But when the divide ratio is fractional, the fluctuation is very small. What's the reason?
Thank you for your reply! If I want to test the phase noise from a divider, I think I should add a clean input to the divider input and then test the phase noise from the divider output by a spectrum analyzer.
Is that right?
The thinkness of metal can be found in assura profile. But I still don't know where to find the thinkness of substrate, epi layer and metal 0. Do you know how to find these information now?
Re: How to get specfication from PDK for ASITIC technology f
Hi all,
The thinkness of metal can be found in assura profile. But I still don't know where to find the thinkness of substrate, epi layer and metal 0. Do you know how to find these information now?
Hi fanshuo,
The thinkness of metal can be found in assura profile. But I still don't know where to find the thinkness of substrate, epi layer and metal 0. Do you know how to find these information now?
Hi DoYouLinux,
I'm now using ASITIC to build inductor. And i encounter the same problem with you. I think your method (replace metal 1 with metal 0, metal 2 with metal 1 and so on) is not consistent with the author's intent. The metal0 mentioned by the author is embeded in epi layer, so i...
Hi, all
As we know, we can predict VCO phase noise using hajimiri's LTV model. And I have read his papers, where he defined a useful function called ISF to calculate phase noise. But I still don't know how to get the ISF from simulation. Do you obtain it by PSS or by TRAN simulation? As I...
Hi, JoannesPaulus. If you want to know how much phase noise your SDM contributes to the whole PLL, you should know exactly how much quantization it has. So if anyone know, please help!
Hi all,
When I use simulink to simulate a MASH111 SDM for pll, the output are digital for example ...-2,-1,0,1,2,3..., and I want to convert this value to output quantization noise. The code I used to do convertion is as follow:
Fref=1e6
NFFT=8096
SIMOUTave=mean(simout)...
Hi,all
Recently, I read a paper "A 975-to-1960MHz Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 44.5 Prescaler for Digital TV Tuners .pdf" I don't know how to measure and get the picture below, does anyone know?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
