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Recent content by hhlin

  1. H

    Multi-Chip Module Testing Articles

    Hi， Please help to download two articles about MCM testing: Designing Self-Testable Multi-Chip Modules **broken link removed** An Effective Multi-Chip BIST Scheme **broken link removed** Thanks! Hailin Huang.
  2. H

    Metastability and simulation

    disabling timing checks selectively Refer to the Synopsys Solvnet article https://solvnet.synopsys.com/retrieve/022278.html Control Timings in VCS VCS/VCSMX can disable module path delays as well as timing checks at various levels of granularity viz. on the entire design, on a specific...
  3. H

    IP Qualification Guidelines

    ip qualification guidelines Hi Everyone, Does anyone know about the "IP Qualification Guidelines"? And how or where can I get more detailed information? Thanks!
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