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hi, viswanadh_babu
Thanks for your guide. is_clock_pin of the CK pin of this cell is false. I look into the libraray description, CK pin has clock attribute. And CK pin of other good cells have this attribute ture. Why the is_clock_pin of this cell is lost?
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I try to set...
hi,
my DC/PT check_timing report said that there are unconstrainted pathes in the design. After I checked the pathes, I found that some registers behind a gating cell is not constrainted. clock does not pass the gating cell which is generated during synthesis. Cound some tell me why this...
Hi, kornukhin
Scan chain and DFT is not included in the netlist (impl).
impl has DFFs. They all are matched with ref.
*********************************** Matching Results ***********************************
29567 Compare points matched by name
1 Compare points matched by signature analysis
0...
I use *.db files. These black boxes are cell power pins like VDD, VSS. They are not compared during verification and they are not used by other compare points. So I think they will not affect the result. I don't know why these pins are inclued in the lib and how to get rid of them.
Actually I...
Hi,
I did a formality between RTL and DC netlist (before inserting scan chain and DFT). There are 48 fail points. 16 of them are power pins like VDD and VSS. I think they can be ignored. But there are 32 points which are a group of data bus registers. I can not find what cause these points fail...
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