Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Before physical design the sdf file generated by PT will include the interconnect dellays (which are modelled) for the timing verification
spef file generated by Astro will contain the exact delay information about the delay
.lib file contains the following
all parameter units like area, time power...(in um, ns, nw)
the timing and power information of the different gates.
wire load model(like 10x10, 20x20...)
these information is used in the synthesis process
using library compiler .lib...
when we know the impulse response of LTI system, by convolving the input with the impulse response of the system we can find the response of the system for that input (similarly you can find the response for any input with the convolution).
this is the mathematical...