Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by hemanth

  1. H

    synopsys Error: no license found contact server?????????

    the procedure we do is this > cd /cad/synopsys/scl/amd64/bin >./lmgrd -c synopsysLicense > lic.log
  2. H

    Design Kit for Cadence

    check out this one, i think you can get cadence design kit https://vcag.ecen.okstate.edu/projects/scells/download/
  3. H

    blocking and non-blocking statements in verilog?

    blocking vs non blocking verilog check out this one, hope this one is useful https://www.asic-world.com/tidbits/blocking.html
  4. H

    synopsys NanoTime help

    synopsys nanotime Path mill user Guide
  5. H

    synopsys NanoTime help

    nanotime user guide Nano Time User Guide
  6. H

    Clock Tree Synthesis and RTL synthesis

    Re: Clock Tree Synthesis clock tree synthesis has to be done separately. It is done in the physical design after standard cell placement
  7. H

    sdf generated by Astro and PT,any difference?

    Before physical design the sdf file generated by PT will include the interconnect dellays (which are modelled) for the timing verification spef file generated by Astro will contain the exact delay information about the delay
  8. H

    Description of synopsys library

    .lib file contains the following all parameter units like area, time power...(in um, ns, nw) the timing and power information of the different gates. wire load model(like 10x10, 20x20...) operating conditions(PVT) these information is used in the synthesis process using library compiler .lib...
  9. H

    Requires .tf and .gds for astro tool

    check out these links https://cc.ee.ntu.edu.tw/~cchen/design_flow/ https://vcag.ecen.okstate.edu/projects/scells/download/MOSIS_SCMOS/latest/
  10. H

    How can I get the netlist for ASTRO

    also check this link https://vcag.ecen.okstate.edu/projects/scells/download/MOSIS_SCMOS/latest/
  11. H

    convolution and correlation

    convolution: when we know the impulse response of LTI system, by convolving the input with the impulse response of the system we can find the response of the system for that input (similarly you can find the response for any input with the convolution). correlation: this is the mathematical...
  12. H

    Difference between FPGA and CPLD

    CPLDs are buit with PROMS where as FPGAs will not contain PROM and theres architecture also differs
  13. H

    How can I get the netlist for ASTRO

    check out this link https://cc.ee.ntu.edu.tw/~cchen/design_flow/
  14. H

    Physical design in design tool ASTRO

    Re: Physical design check out this link https://cc.ee.ntu.edu.tw/~cchen/design_flow/
  15. H

    How can I get the netlist for ASTRO

    use auVerilogToCell command for readign synthesized gate level verilog netlist

Part and Inventory Search

Top