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No, the latch also have a lauch edge. If a latch's enable signal is high active, the negative edge is the lauch edge.
Setup time: the data must be stable time before the edge
Hold time: the data must be stable time after the edge
To DFF, I can create a clock, and define the min & max library. The DFF setup & hold time problems can be solved by DC. But it is latch, how to deal with it?
I search it in synopsys sold, but nothing found.
In my design a latch is needed, but its enable signal is generated from several input signals. and the data signal is generated from several input signals too.
It brings setup & hold time problems.
How to write a synthesis script to deal with it?
I found hold time violation when doing primetime STA, but no hold time violation found in Astro. So I have to do DC reoptimize_design. And some max_transition violation is found in Astro, but no max_transition violation in primetime STA.
Why the timing check isn't match?
Thanks!
From SOLD the "reoptimize_design" command often be used at postlayout netlist reoptimize. As you posted, the DC command reoptimize_design can not be used at postlayout netlist after CTS? It only be used at postlayout netlist before CTS?
Is it right?
I finished synthesis by using DC, And i finished P&R(0.18um) with CTS.
But when i do STA after "set_load, read_sdf, read_paractics" , i found some max_transation & setuptime violation. So i reoptimized the design, STA pass.
How can i feed this change to P&R tool? Because of CTS, the new...
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