Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi ,
After reading some documents, the refresh cycles equals the row number. That means the same row in all banks are refreshed at the same time.
As for the SDRAM you ask, I am not sure why the refresh count is still 4096. My wild guess is that it is more like a standard (either 4096/8192)...
I am not an expert in SDRAM, but as far as I know, the refresh cycles is determined by the internal structure of Bank/Row, and it is not always 4096, like the one I am using now, IS42S32160F, it needs 8192 cycles every 64mS.
There is an internal refresh address generator which generates the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.