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ocd commander protocol interface
hi,
what is the relationship between RDI protocol and JTAG interface?
and what about Macraigor' OCDcommander, is it related with RDI?
thanks for help.
now i am working on TMS470 with IAR EWARM. and when i do the debugging with wiggler, there will be a pompt 'JTAG ERROR: hold in reset state' often.
is it related to JTAG reset status by TRST ?
( actually TRST is pulled up in the Evaluation board and you can pull it down to the...
ye, i have reversed the GND/VCC.
what i want to aks is, what will happen to JTAG interface if TRST is always connected to GND during the whole debugging?
can the debugging work fine in theroy?
iar debug release 比较
there are four option : release/debug in RAM
release/debug in FLASH in IAR EWARM.
what is the differences between release/debug ?
trst pin
thanks for info.
i checked the datasheets of one MCU, TRST is active low. so it should be connected to GND in normal case, right?
if it is always connected to VCC, so what will happen to the JTAG interface and debugging?
jtag trst
my wonder is how to manipulate the TRST signal in wiggler.
in theroy, should it be connected to high level or GND?
and what is that signal for?
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