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a bias circuit
hi
i think it is negative feedback, to stable the stable the Im3.
eg. Vg decrease Im2 decrease, corresponding with Im5 decrease,but Vgs3 increase,so Im3 increase.
then feedback induce to stable Im3
output and input of cmos inverter shorted
1.if no signal input, the output voltage level will be the Vdd/2, just be the Vdd.Rn/(Rp+ Rn).
2.if 0 or 1 is the input ,and many inverters is cascade,they will be osillater.if only one inverter, it will be just resistor divide Vdd voltage.
3.on upper...
vnu=vgsmb10-vdsmb8+vgsmb8
other trace vnu=vgsmb10+vdsmb6
you must satify: vdsmb6=-vdsmb8+vgsmb8
so the w/L of mb6 should be smaller . mb4 will be cut off. so vnu=0
if the w/L of mb6 is large, vdsmb8 is large, mb10 is at triode region.
so vnu= vgsmb8 or so. it is too low.
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