Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by heba_saleh

  1. H

    Verilog-a cyclically dependent error

    simulator lang=local parameters I0 out x0 x1 nand2 subckt nand2 out in1 in2 V6 n3_1 gnd vsource type=dc dc=1.3 M7 out in1 n4_4 gnd n w=0.0001 l=1.3e-007 M9 out in2 n3_1 n3_1 p w=0.0001 l=1.3e-007 M10 out in1 n3_1 n3_1 p w=0.0001 l=1.3e-007 M8 n4_4 in2 gnd gnd n w=0.0001 l=1.3e-007...
  2. H

    Verilog-a cyclically dependent error

    Dear all I am new to verilog-a and symicaDe tool .. I want to write and read data from a file so I copied a simple veriloga code from the manual. `include "disciplines.vams" `include "constants.vams" module fileexample; integer mcd1 ; integer mcd2 ; integer mcd ; analog begin...
See more

Part and Inventory Search

Back
Top