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bigdogguru, i'm sorry for my mistaske - i was first read your PM and later the forum. but my questions in pm are valid :) DDR is not the problem - the DDR test pass in all modes. The problem is FLASH:
Can you regenerate project with flash test enabled?
look at www.opencores.com? i think 8086 was implemened in some project. may be... if i'm not wrong... :?: but to decompress video - this is not so easy. and what is the compression of video?
may be this will be helpfull. if u cant find source codes - send me PM, i will send u the files. in this project u must write (define in ram) your own frame buffer, this is only controller for hs, vs, blank and pixel position.
u must read more about division - the successive methods in FPGA are not so much. i develop my own full pipelined divider (non-restoring algorithm), but if u want to use more than 16/8 bits the delay between carry in-carry out of SLICEs is too big and the speed decrease (may be under 150Mhz). If...
hi again! @bigdogguru, thank you for support, i realy have no alternatives to test this example on Xilinx board. The kit is this - Digilent Spartan-3E Starter Kit (500K), rev D, and u are right - in EDK i can select Xilinx as manifacurer, but i have no option for Digilent version. Realy i was...
ok, the kit is from digilent. i will verify ucf file from start to end, but peripheral test was passed correctly - leds was blinking, switches are read correctly. tomorrow i will post the results for FLASH. and the other question is: memory controller - address bus 24 is controlled by CPLD. may...
hi! i'm new in EDK, please excuse me if the question is stuped. i have a little problem - i use EDK ISE 11.4 to generate microblaze system with BSB. ok, next step i test_mem project generated by SDK. i run it on target (spartan-3e starter kit, rev D) and ddr test pass successfully, but FLASH...
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