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Recent content by hayang

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    what is the difference between Utopia and spi3 interface

    I heard these 2 are very similar indeed although for different applications. thanks
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    SystemC , Systemverilog , vera , specman...

    i don't know why someone said "systemVerilog is slow", from general understanding, using any third party EDA tool will make the simulator slow. But if we use systemVerilog we don't need any third-party tool through PLI interface. so, using systemVerilog is faster. is my understanding correct?
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    how is the current ICjob market in Toronto and Ottawa/Canada

    current engineering job market in toronto thanks, Mr. cool, for the kind reply, i graduated from the best engineering school in China, and Carleton University of Ottawa. I believe I am one of the best engineers. I am now a verification lead in a US based start-up company. do you know some good...
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    how is the current ICjob market in Toronto and Ottawa/Canada

    ottawa fpga engineer hi all: I am an experienced ASIC/FPGA engineer with about 5-6 years of work experience. and I worked for CISCO as hardware engineer for 2.5 years. I went back to China and work for some time, now I am considering going back to Canada. But I heard the job market is poor. Is...
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    an altera stratix device question

    hi, all: in altera stratix fpga device, is the relation between Pin number and I/O bank number fixed? can we program it? in another word, if the pin location has been fixed, do we have the flexibility to connect it to wanted I/O banks? thanks harry
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    stratix Enhanced /Fast PLL, Gclk, Rclk question

    hi, I am new to stratix FPGA design, maybe my question is too simple. what is the relation between Enhanced/Fast PLL and Global/Regional clock? our current design uses a lot of clocks, and the Global clock number are not enough, so we need to use Regional clocks, but the pin locations have been...
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    how to start to learn Synopsys Design Compiler?

    synopsys dc manual attend the synopsys course "chip synthsis workshop", it is pretty good to start from.
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    The explanation of false paths

    Re: false path In Synopsys Design compiler, a false path is a path for which you will ignore timing constraints. for example, when crossing different asynchronous clock domains. Under this situation, you will have to disable the timing-based synthesis on this path.

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