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hai,
i designed a system , which get reset from the parallel port of pc........
which is asynchronous. But i sampled it with the faster clock in the design. Do u
think that now this reset is synchronous. How can we differentiate syn and asyn resets.
please help me...........
hai,
can any body answer my doubts...
1.what is metastability,when does it happen and how to recover from m.s.
2.How synchronisation is done between two clock domains for different signals.
please help me.......................
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