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Recent content by hareeshP

  1. H

    VHDL state machine execution

    Hi all, I have posted a portion of a code. Which is a state machine. I want to know how the below code executes. In the code, when this statement is ture if scl_falling_strobe = '1' and bit_counter = 8 then the code executes SEND_ACK1 state or it goes on executing sequentially (next...
  2. H

    MAX 10 pin assignment error

    Hi all, I'm currently using the MAX 10 (10M02SCU169A7G) for one our project. In MAX 10 (10M0) fpga the pin C4 and C5 are nSTATUS and CONFIG_DONE respectively. And we have used this pin for some other purpose also. As per the datasheet both these pins are dual purpose pins. When i do the I/O...
  3. H

    SignalTap waiting for clock

    it is running, and i verified with oscilloscope also.
  4. H

    SignalTap waiting for clock

    No i probed using the oscilloscope, and it is coming properly.
  5. H

    SignalTap waiting for clock

    Hi all, I'm using Altera SignalTap for monitoring the pins of fpga. We have two clock one for fpga which is 20MHz and another one is a 50MHz clock(we call it ifc clock) which coming from processor. Some registers are initialized based on the rising_edge of ifc clock and the register transmission...
  6. H

    modelsim error during RTL simulation

    I got the solution, the test bench entity name was incorrect in compile test bench. everyone was once a beginner....
  7. H

    modelsim error during RTL simulation

    Hi, I am not able to debug the issue. what you mean by tb in testbecnh.vhd?
  8. H

    modelsim error during RTL simulation

    hi all, I'm getting an error while doing RTL simulation on quartus, the comments are pasted below # Reading C:/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl # do po_run_msim_rtl_vhdl.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model...
  9. H

    MAX II CPLD performance

    Hi all, does the max ii cpld EPM570GF256C5N and EPM570F256C5 are same??
  10. H

    Vhdl when else statement error

    so how do i solve this. can you please help me.:-(
  11. H

    Vhdl when else statement error

    hi, please anybody help me with the issue...:cry::cry: ifc_ad8_15 <= "ZZZZZZZZ" when cpu_rst_n and (not rst_hold_f) and (req_rst_r when (req_md_r = "11") else '1') = '1' else rcw_src(0 to 7) when boot_override_r = '1' else "ZZZZZZZZ"; showing the same error Error (10500): VHDL...
  12. H

    MAX II cpld volatile programming

    thanks for your reply. I have one more doubt, i have read about cfm( configuration flash memory) it is used for isp( in system programming). Does it mean cfm can only be programmed while the board is currently running?
  13. H

    MAX II cpld volatile programming

    Hi, can i do the volatile programming in max ii cpld?
  14. H

    Reading ufm of max ii

    i got the .pof file from the ufm, But it has a memory size of 15KB. When i converted the .sof file of my program into .pof through quartus software it shows a memory size of 353KB. does max ii compress the file inside ufm?
  15. H

    Reading ufm of max ii

    ok. how the ufm is accessed through internal logic?
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