Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Hards

  1. H

    Endcap, Decap, Subcap - material, the functionality of them

    end cap cells Hello Guys, Does any one has material regarding Endcap, Decap or Subcap then please share. Or can anyone tell me the functionality of them ? I really need it. Please share it. Thanks in advance Hardik
  2. H

    CTS question in Astro - how do we specify "separate tre

    CTS question in Astro Hi guys, I am new in Astro. I was using Magma tool previously. I want to know that how do we specify "separate tree" in asto. I want to specify separate clock tree for macros. Please help me. - Hardik
  3. H

    Via redundency and island

    Island is something minimum area violation. For example, piece of M2 should have .50u2 minimum area. If there is a metal piece in your design which have area less than .50u2 then there will be an island violation. And I hope you are clear with the via_redundancy from above explanation. Via...
  4. H

    65 nm Leakage Problem

    Please go through this doc
  5. H

    The information about the Flip-Chip

    Re: Flip-Chip Thanks for your all answer. Can any body give me the material regarding to it. Thanks Hardik Added after 1 hours 42 minutes: Hi , I have one more question.. Do we require extra library for the bump cells like Standard cells and Pad cells. ?? Thanks Hardik
  6. H

    The information about the Flip-Chip

    Hi, Can any one give me the material regarding to the flip chip. What is flip chip ?? Please let me know ASSP. Thanks Hardik
  7. H

    I want good material on STA

    Hi .. This will help you..
  8. H

    What are differences between clock buffer and buffer?

    Re: clock buffer Generally there are separate entity in the library are there like CLKBUF and CLKINV but In 65nm liberary there is not any entity like CLKBUF or CLKINV so could anybody tell me which buffer of inverter should we use for clock tree Hardik
  9. H

    Need a tutorial for entire digital design flow

    Re: Digital design flow This will really help you ..
  10. H

    Suggestions of materials about crosstalk

    Re: Crosstalk Hello All Thaks for you reply I have also found some good material on crosstalk
  11. H

    Suggestions of materials about crosstalk

    Can any body provide me the good material on Cross-talk. I want to elaborate why Buffeinin and resizing the cell can help to reduce the crosstalk. Pleas provide me good material on that. Thanks Hardik
  12. H

    What are the details about level shifter and isolation cells

    Re: multi voltage flow hello good discussion is going on here.. thanks hardik
  13. H

    how to practice PERL language

    Hi.. Thsi will help u Hardik
  14. H

    Looking for information about multicycle path

    timequest multicycle When a data path is too long that can not be completed in one clock cycle then for that perticular path we have to define mulfi-cycle path.
  15. H

    Material on Clock Tree Synthesis in Magma

    Can any body provide me the material on Clock Tree Synthesys of Magma.. It should be in deep It should include all the topics like - clock phase - skew phase - skew group - generated clock - skew anchor etc Its urgent please .... Thanks in advance Hardik
See more

Part and Inventory Search

Back
Top