Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by happyree

  1. H

    need help with RF circuit post-simulation problem

    I redraw one part of the layout and simulate again, the phenomenon disappear.
  2. H

    Help me fix Calibre LVS extraction errors/warnings

    unattached label calibre extraction You are right, in the "calibre.lvs" there are commands: TEXT LAYER 45 ATTACH 45 metal6 PORT LAYER TEXT 45 and TEXT DEPTH PRIMARY PORT DEPTH PRIMARY
  3. H

    need help with RF circuit post-simulation problem

    Hello everyone! when I do post-simulation with assura extracted-view after the lvs and rcx step, I find an odd problem. As is showed in the picture a rf_mim cap is directly connected to the gate of a MOS transistor. But their DC voltage are different. And it seems the rf signal of the two...
  4. H

    Help me fix Calibre LVS extraction errors/warnings

    unattached label on layer metal Thank you, pit1000. I 'm sorry that I am still not very clear about what to do, because I do not know much about the simulation tools and the rules till now. There are only pins on layer Metal6, and no other labels in the layout. Should I change the lvs...
  5. H

    Help me fix Calibre LVS extraction errors/warnings

    Hi everybody, I'm designing rf front-end circuits recently. when I finished lvs with calibre, there are some extraction warnings as below: Extraction Errors and Warnings for cell "ind_std$$180566060" ------------------------------------------------------------ WARNING: Unattached label...

Part and Inventory Search

Back
Top