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Recent content by happylbd

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    example needed for using mailbox in multicore microblaze platform in xilinx V5 FX130

    thanks so much for your help,with the help of these document i think i can solve my problem
  2. H

    example needed for using mailbox in multicore microblaze platform in xilinx V5 FX130

    i search the xilinx website，but cant find any useful resource on mailbox ，hoping that you can give me more help，a website link，a example. THX
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    example needed for using mailbox in multicore microblaze platform in xilinx V5 FX130

    i was working on a multicore microblaze platform ,i want to use mailbox to deal with the data communication between the two cores(microblaze) my problem is that i have no idea how to config mailbox,i hope anyone could kingly show me a example THX
  4. H

    [SOLVED] how to count clock cycles in microblaze（using ML510-virtex_5 FX130）

    Re: how to count clock cycles in microblaze（using ML510-virtex_5 FX130） i've found one way to figure it out. let the EDK program be part of a ise project ,then count the time by a counter in verilog code. but i found the clock cycles is not stable ,it changed every time i run the program keep...
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    [SOLVED] how to count clock cycles in microblaze（using ML510-virtex_5 FX130）

    i'm working on microblaze to realize a multi_core platform on which i'm testing FFT,in order to calculate the speed up ratio,i need to know how many clock cycles it takes. C code is used in microblaze ,i'm wondering if there is some specific function in C can calculate the clock cycles. waiting...
  6. H

    How divide two numbers in verilog

    you can use a divsion IP core to realize it because division and multiplication can not systhesize in ISE or QUARTUS
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    verilog code for soft output viterbi decoder

    in FPGA ，the computational complexity of euclidean distance is largee than Manhattan Distance so i think Manhattan Distance will be a better choice concerning the soft viterbi,you will need quantitate the code 1 1--(-4,-4) use 3bit 0 0--(3,3)
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    8-bit adder help with my current code.

    i think code of "c_out" can write ao follow: and(t1 , a , b); and(t2 , a , c_in); and(t3 , b , c_in); or(c_out , t1, t2, t3);
  9. H

    FPGA board for starters

    Xilinx University Program the link above is about the Xilinx University Program the board related to this program might be a good choice, cause you can find lots of reference and examples which will do you great help
  10. H

    hardware so simulation

    Do you mean the tool-system generator in MATLAB simulink for Xilinx
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    Help needed for 16X2 LCD on board ML405

    i got a project on hand and i need to show something on the LCD,bad thing is that this LCD can only work under 4bit mode.I googled a long time but can't find any demo verilog code for 4 bit mode. I wish anyone can help me,show me a verilog code or how to figure it out. thanks a lot! PS:the LCD...
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