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Recent content by haosg

  1. H

    Can you stretch a clock pulse by N?

    question of clock? may be he want stretch a high-pulse to N time width. but this is too difficult.
  2. H

    why moore is safer then mealy?

    if the input is also synchronous with the clock that triger state register no glitch occured.
  3. H

    Which of these is synthesizable: task or function?

    q of task and function? yes, function dont support timing definition, but task support, generally they both can be sythesized if the have no timing definition and un-synthesible syntax.
  4. H

    A question about synthesis

    synthesis set_case_analysis you should set_case_analysis 0 TEST_MODE in functional STA, and set_case_analysis 1 TEST_MODE in test mode STA.
  5. H

    what's "a Tiehi and Tielo gate" ?

    tiehi cells tihi will output a 1'b1( hige level), instead of connecting VSS to standard cell's input. tilo will output 1'b0.
  6. H

    How to wrap a black box with Synopsys Shadow LogicDft ?

    difficult dft question yes, DFT compile can automatically add shadow logic auto fix logics.
  7. H

    Help me with Clock Tree Synthesis

    CTS challenge create_generated_clock output -source main_clock in top level, thus Astro would make that output have same waveform with main clock's sync point like DFF's CK pin.
  8. H

    Statement unreachable (Branch condition impossible to meet)

    how do you say unreachable in french it is only a combinational loop, so it is only warning. so I don't know why the "unreachable branch " occured,
  9. H

    how to synthesize gated clock??

    gated clock synthesis rtl compiler create_generated_clock clk -source clkin -divid 1
  10. H

    what is the diff between dual port & single port RAM?

    the fifo generally use two ports register-file. it have seperatly write and read ports. the single ports have a shared R/W ports, the dual ports have two R/W ports, each can read/writed.
  11. H

    Where is network processor generally used?

    network processor Hi, who know the where network processor is generally used.
  12. H

    verilog code of asynchronous FIFO ram?

    verilog fifo yes, it have been a general circuits. and the structure is very simple.
  13. H

    Consider a 2:1 mux , what will output if sel is"x"

    sel.is in simulaiton, the output should be x. of courst , there are no x state in real circuits.
  14. H

    Why coreConsultant can generate a readable Verilog file?

    coreConsultant question? coreConsultant can only generate ecrypted codes.
  15. H

    Method to provide constraints in DC

    the i/o input/output delay should be decided by the chip's environment
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