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Can a reference from 2 pixels to a palette map like the NES does be somehow protected? Has Nintendo invented this ?
I would like to know so i can sleep well :-)
Hello,
i try to build something tile-related and i need to know if i hurt someones feelings if i do this :smile:
The problem is the part where the 2 pixels from the tile-detail-map encodes the final color via the color map/ palette map. I saw that the C64 has a different solution from Master...
http://martin.hinner.info/vga/timing.html
http://tinyvga.com/vga-timing/640x480@85Hz
**broken link removed**
This are the links i found regarding VGA signal timing.
I intend to halve the line resolution so that an AVR can generate the (doubled) pixel clock with an 18MHz clock source.
The signals are generated by an AVR and the resolution is 640x480@85Hz.
There are some 3 websites with roughly the same timings for this resolution - but they seem to have a difference of 30 pixel for the start of the visible line after the horizontal back porch. This could be a flexible...
Hello guys!
I try to program a VGA test pattern generator and i have seen that the whole thing is divided in horizontal lines. For example the v-sync is 3 lines long.
Now i do not know how to start the horizontal line after the v-sync-line is done - this should be after the frontporch of the...
In the book "EMC for Product Designers" by Tim Williams stood that the maximum allowed loop area formed by 74HC logic family should not exceed 45 cm2 at 4 MHz.
But is that the loop are of all connections from one package summed up or just per single trace ?
Hello,
does someone know how strong the electromagnetic emmissions of a homemade double-sided board (no ground plane) could be if there are some 74HC family, an 8051 cpu with quartzoszillator (6 MHz) and some sram and eeprom chips ?
The layout is not optimized, there is not an optimal return...
This 8051 type has some nasty pinout, the two signals under the oscillator should be /RD and /WR but i saw that the oscillator is in a metal case that is connected to its GND pin so it may be not that bad for the trace under it.
The decoupling capacitor at the right side of the CPU is bad...
I want to fit this PCB in a box with conducting walls of some kind, but the top side will be open at runtime because there is an I/O board stacked above the CPU board. I think i sandwitch some metal plate between the CPU and I/O board and ground it like the case via a 1MOhm resitor to the ground...
Hello,
could someone tell me if there is a EMI problem to expect with this 8051 circuit layout ?
It runs at 6MHz clock and the buses should run at 500kHz.
I messed the placing of the decoupling capacitor at the 8051 cpu, i think it should have been above the CPU and connected via a top layer...
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