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Thanks! I got a bit more clear now.
But I don't know what's the protocol to substract. It depends on actual design, right? Sychronous or Asychronous...
If there is the data timing diagram, it may be much easier to understand.
Would you please show a true design, and calculate the percentage of...
DSP: TMS320C6713B
FPGA: Xilinx V7
interface: EMIF
Data Bus: 32-bit
Bus clock: 100MHz
Then how to calculate the effective bandwidth?
Could anyone tell me the method...
Normally we pull the ENABLE to VCC through a resistor, instead of directly connecting to VCC as the pic shows.
I wonder the benifis of this resistor. Anyone could help me?
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Physical layer link issue. I judge the issue from LED status. When link up, LED on RJ45 connector is on, while it's off when link is down. When issue happened, ping I210 fails either.
It should not be SI problem, because once replug the cable the link would restore, and issue never happens...
I met with a problem when design with the ethernet controller I210(Intel chip). When LAN port connect with several brand of switch, the link failed after power on, and could be restored by replug the LAN cable. When the LAN port connect with other switch, the problem won't happen.
I have no...
What's the difference if replug LAN cable at board side or at switch side
I met with an issue when design with Intel I210. Connect my board and a switch with LAN cable, then power on the board, sometimes the link fails, and can be restored by re-plugging the LAN cable.
The issue happens when...
I am reading an IC datasheet, seeing PCI Express physical functions and PCI Express virtual functions. What are them?
I don't know much about PCIe.
Would anyone please explain to me?
When I place GND in capture, it appears two libraries on the "place ground" dialog block which are" CAPSYM" and "Design Cache".
I have some questions as below:
1. CAPSYM: what's the difference between GND & GND_POWER ? how to use them?
2. Design Cache: why are there more than 5 GND in the...
Thanks for your reply.
It is placed on TX side just by convention?
I thought it was for some kind of SI concern.
Otherwise the AC capacitors could be placed anywhere easy for layout, why make a convention to limit. Is there any advantage to place on Tx side?
When study PCIE 3.0 spec, I find it describes that the A.C capacitors must be placed on the Transmitter side of an interface that permits adapters to be plugged and unplugged.
Also I know the coupling capacitor always placed on the transmitter side.
But I don't know why. Anybody please help me...
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