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I'm adding the delay at the testbench and not the design.
I tried working with negedge and i added "clock -both_edges clk" in the TCL file but the assertion is failing because its evaluated at both edges two.
Hello everyone,
I am an electrical engineer student and now I'm in an internship. I'm working with jaspergold and I need to delay a signal for a portion of the clock cycle (half cycle or less or more) but I am blocked .
Here is one of the ways I tried :
assign #0.5 ack_d = ack
I also tried...
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