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Recent content by ha43100

  1. H

    about modelsim simulation problem

    the design is successfully compiled,when i start simulation with modelsim,it happens as follow: # ** Fatal: Unexpected signal: 11. # ** Error: E:/share/post_layout_password/count18.v(14137): Verilog Compiler exiting # ** Error: C:/modeltech_6.4/win32/vlog failed. # ** Error: Sub-invoking of...
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