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Hello ecasha,
To learn basics of radix-10 decimal multiplication and its implementation purpose kindly see the links
**broken link removed**
https://www.cs.princeton.edu/courses/archive/spring09/cos226/handouts/Algs3Ch10.pdf
https://www.imm.dtu.dk/~alna/pubs/asil06dec.pdf
Kindly check this...
Refer books like Basic Antenna Principles for Mobile Communications Peter Scholz,Antennas for Base Stations in Wireless Communications by Kwai-Man Luk and Zhi Ning Chen
Hello dpaul,
Thank you very much for your valuable response......above given link is surely very useful one for stuck at faults. In that discussion faults injections signals and its syntax followed by vhdl method. same like that is it possible to inject the faults in verilog ???
Hello,
Can anyone suggest me how to implement stuck-at-faults (stuck-at-0 or stuck-at-1 faults) using FPGA. In my coding i have used stuck at faults using force the signals. Its able to done successfully in simulation level..but implementation its not able to synthesis using FPGA..so can anyone...
If i made any confusions means sorry to all
i am not used any standard tools so far.....in future days i am going to access standard tools through institution.....before that my plan is searching any other testability measurement tool......through google search today i found one tool for...
if i confusing you means really sorry........
yes my aim is to perform testability measurement by using particular circuit netlist(gate level),then by applying various faults to the circuit & apply ATPG algorithms...then we can get testability measurements like fault coverage test vector...
Thank you for your reply....
no, generating test patterns for various faults is one of my idea... my another idea is using various faults to calculate the fault coverage,point of Controllability,point of observability measurements & estimation of test vector length....
So that i need a...
In my opinion for measuring inductance better method is
(i) connecting a resistance in series with the inductance, thereby measuring the time constant, from which the inductance value is calculated.....because in this method Connect the inductor coil in series with a resistor whose...
thanks for your valuable suggestion....
I am asking what are the tools used to calculate the fault coverage,Controllability,observability measurements & estimation of test vector length???
please can anyone tell me what are tools for testability measurements ???
thanks for your reply....
yes,testability measurement means that for calculate test coverage and also Controllability,observability measures & estimation of test vector length.......
Is there any testability measurement tool available for podem or D-algorithms???please can anyone tell me what are tools for testability measurement ???
Hello dpaul,
Thank you very much for your valuable response......yes for generating test patterns, D-algorithm/podem algorithm steps by using verilog.
and till now I am not used ATPG tools...I am planning to use ATPG tools...but before going use ATPG tools,need to simulate D-algorithm/podem...
Hello,
For generate test patterns how to apply d-algorithms/podem algorithms steps using verilog??
Please can anyone tell me the procedure how to apply d-algorithms process using verilog???
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