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Recent content by guntherleet

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    Layout Parasatic Exctraction Filter Setting

    especially in advanced nodes and high-frequency applications, the parasitic is significant and resolution of 10fF might be not high enough in my opinion. 0.01fF is realistic and in big designs, those parasitic accumulate very fast.
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    Analog and digital ground and supply voltage seperation in IC

    using ! make global net and is not recommended, you can use vdda and vdd for example to represent analog domain supply and digital domain supply. there are layout layers designed for this issue of separated supplies that enable you to connect to different substrates in the same layout(PSUB2 if...
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    strongarm comparator

    Things you can consider checking are: CM sensitivity - how input signal CM effect decision time/resolution The effect of the frequency of the different phases(CLK) The sizing of positive FB transistors and the parasitic capacitance on the output node should limit your comparator speed Noise...
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    I cant find PACmag in cadence

    Hey, try using regular vdc instance it should have PAC parameters
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    DAC Layout

    Hey, M7 to M3 is pretty far, you can try enhance the layout with shielding the clock's routing with bottom vssa plate(and even side&top shield). I would also see what happens with r-only extraction to examine if it cc issue.
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    simulating opamp virtual ground

    You connected two common source amplifiers in parallel. introduce a current tail providing both branches to create differentially
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    dynamic two stage comparator

    MX is like a buffer between the sensing stage to the latch stage. the differential input (INN/INP) create differential current discharging the capacitance on nets FN and FP in a rate ~(proportional) t , with the introduce of Mx the t required to activate the latch is longer then in different...
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    How to improve the performance of the circuit?

    I was referring the device self capacitance, you correct in the sense that the overall parasitic is more dominant because structures become denser with narrower routings and contacts also because the device self capacitance getting smaller so in percentages the parasitic play more critical roll.
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    How to improve the performance of the circuit?

    For analog designer to migrate a circuit to more modern process (alike 5nm as you mentioned) is usually will make the circuit perform worse. Transistors behavior much more interwind with higher order effects, and a lot of time you lose some degree of freedom with choosing the physical size of a...
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    problem imagening the meaning of phase noise definition -70dbc/hz at 10Khz

    Its measure of PSD, think of regular WGN, its random in time but have PSD = const for all frequencies.
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    Factors related to improvement of eye diagram

    Hey, How you measuring the jitter? you sampling after a channel? Eye diagram contain data about random jitter and deterministic jitter as well

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