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Thank you Dana, for going through the effort of simulating the PM. I appreciate it.
I have switched to a different topology, which is simpler and stable.
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Hi FwM,
thanks for sharing. it's possible, but in this case, I have a sine-wave driver 10mV-rms from a function generator.
hi dana,
Q) Sounds like this is not in the sim, but bench testing ?
=> Yes, not in simulations, but bench testing.
Q) What is part number of amp ?
=> AD743
Q) You using JFET because actual input is for electret mics ?
=> The sensor is a capacitive MEMS transducer. The capacitance at MEMS:AFE...
Klaus,
Q) this all makes no sense.
=> my apologies. let me attempt round two.
Q) at which frequency?
=> At 1kHz. Basically I inject 10mV-rms 1kHz since wave at the JFET input and observe Vout = 500mV-rms at the output. Gain being = 1+Rf/Rs = 50V/V = 34.15dB.
Upon power up, the output is...
hello,
I have build this amplifier. In lab, I am applying 10mV rms at the input. At output I see 400mV-rms at time=0s. And over 3.5minutes, the output rises from 400mV-rms to 500mV-rms. The expected output is 500mV-rms. After the output crosses say 504mV, the amplifier becomes UNSTABLE.
I...
I have the same question.
Gautham, when I swapped models from level 49 to level 3 (random academic model files found on cmosedu.com), I got more "c" (cgd cgs, etc) in the ltspice dc op sim. I couldn't figure out where it is defined. I mean why type models would impact which "c" to report in dc...
Hello,
I am designing a dielectric sensor which consists of an interdigital capacitor (IDC) at the top layer. I found analytical expressions for an IDC in a 3-layer dielectric stackup and currently debugging my setup. (The theoretical estimate is 40% higher compared to HFSS). Although my...
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