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Recent content by gujaratibhai

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    Change Defaults of Cadence ViVA(Virtuoso Visualisation and Analysis)

    Thanks for pointing it out. I have observed the interdepedancies but in the past I could never get the VIVA trace to be thick as desired. Your list is very good. I will try it out. Thanks!
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    Change Defaults of Cadence ViVA(Virtuoso Visualisation and Analysis)

    In the directory where you launch your cadence from, have a file titled ".cdsenv". It is there, where I have one following line related to VIVA settings: o viva.rectGraph background string "white" Though for line "thickness", i find this to be not working. The background indeed changes to...
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    Chopping Frequency vs GBW Relationship

    Hi I am doing a post-layout extraction and i have noticed my GBW drops significantly from 200kHz to 100kHz due to large amount of parasitic caps coming from my >2k distributed poly resistor segments. I partially chop my error amplifier (structure: nmos input pair, folded cascode and...
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    chopping amplifier: how does this remove 1/f noise

    Master thesis found at link below seems to be using the same architecture for a fully differential amplifier. I will review and hope it had further insights. Thesis link: https://digital.lib.washington.edu/researchworks/bitstream/handle/1773/22034/Mandic_washington_0250O_10933.pdf?sequence=1
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    chopping amplifier: how does this remove 1/f noise

    Hi FvM, Unfortunately, there is none. The 3 cross switches is all i see. I have also seen results where with chopping enabled 1/f noise gets reduced quite significantly. I just don't understand the knobs on what dictates the improvements and by how much. Thanks, Gujaratibhai
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    chopping amplifier: how does this remove 1/f noise

    Hi folks, I redesigned a 2-stage amplifier but am told to add chopping to it to fight the 1/f noise. I have read about chopping and it's advantages (Enz papers) but they seem too theoretical and have difficulties translating it to *me* using it. I have a snapshot of an existing design where...
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    get switch cap current

    hi shanmei, you may be misinterpreting what i'd call this an equivalent dc current for a cap being refreshed at frequency "f" for a continuous *true* DC current. see if i can explain, Imagine a pulse train from Vref (low voltage) to Vin (high voltage) at frequency "f" with duty cycle of 50%. A...
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    V to I converter stability ?

    hi cmos_ajay, i agree with your statement Rz+Cz should "connect them between th[e] gate of PM7 and drain of PM7". Cz is the compensation cap and Rz would be the nulling resistor for stability if placed across gate+drain of PM7. I bet this is incorrectly drawing schematic in that paper. Though...
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    Comparator offset measurement

    Follow the previously suggested testbenches from other designers, create a measure statement (DC, Transient, etc) and upon running a Monte-carlo simulation, you can assess your mismatch/PVT induced variations of the offset by observation the standard deviations. If you are wondering exactly how...
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    [SOLVED] 30mV systematic offset - folded cascode

    Guys My diff pair was asymmetric. Dumb dumb dumb. Thanks,
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    [SOLVED] 30mV systematic offset - folded cascode

    Hello, This is my second ever post here. I have been a lurker for quite some time and love coming here now and then. Well I am struggling with a 2-stage amplifier design. I am designing a 2-stage, nmos input pair folded cascode amplifier. I am happy with DC gain, GBW, quiescent current, etc...
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    [SOLVED] CONT is VIA for Poly to M1 and also for Nwell?

    Erikl, Thanks. Whenever I see "erikl" responded, I generally read the response just because. Thank you for being wealth of information and actually offering your help to many! Regards, Gujaratibhai
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    How can I find process mismatch parameter Avt

    Hey Raja, In the case your foundry does not provide you this data, you can extract it out by running a set of simulations. In the past, I ran >500 iterations to extract AVT for a device. Here is how the flow went, If you have monte-carlo simulator (ADEXL or BDA), then you can create a...
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    [SOLVED] CONT is VIA for Poly to M1 and also for Nwell?

    Hi folks, CONT (contact) is a via for M1 to Poly connections. And CONT is also the via to connect to Deep-Nwell or PIMP layers. There exists a SiO2 layer exist underneath the poly, correct? Thus CONT for Poly must be shorter than the CONT to connect to the a Deep NWELL underneath? When I look...
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