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Hello,
I am one beginner of monte carlo simulation. I need help urgently.
Now I want to simulate the drain current mismatch of mos transistor with respect to vgs-vth, where vgs-vth is defined as design variable and drain current defined as output in ADE and monte carlo.
Could somebody tell...
I just simulate the netlist with sdf. the netlist is synthesized by using encounter compiler. After the simulation of verilog-XL the error appears:
dc_CLK_Divider.sdf L1058: SDFA Error: Could not find path I1 to O in instance TB_CLK_ Divider.CD1.g2406
dc_CLK_Divider.sdf...
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