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Recent content by gstekboy

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    Static & Dynamic IR analysis operating conditions

    For dynamic IR —> Worst case : process : slow , voltage : max , Temperature : High
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    [SOLVED] Endcap and Decap Usage in P&R

    Hi , For place and route tool tool won’t care physical only cells. The run will go through pnr without any fail.
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    [LEC] Why needed in ASIC flow?

    I will tell you a example, what will happen if you touch clock tree in PnR by adding extra inverter in clock path. Your pnr will go through but what you did was logically not correct ,your LEC will point this
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    [SOLVED] Endcap and Decap Usage in P&R

    Not needed unless you are not running any calibre DRC checks.
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    How to use Synopsys saed 28/32 technology file

    I think what you are mentioning is timing lib. , tech file will be a single file containing process rules.
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    Timing Checks in primetime

    First go with X-talk noise/delay and Transition, then setup and finally hold.
  7. G

    Design has 600 macros, How will you start the macro placement?

    Analyse the macro connectivity , macro to port connectivity, logical hierarchy and start placing manually. (Dont use tool to do manual placement, most of the time it wont be optimal)
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    Dynamic IR drop analysis

    Good PG grid will solve almost all the IR problems.
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    Why def file is needed apart from gds file for starrcxt?

    For that .v.lvs (verilog netlist with pg) can be used, why .def? Also if sub macro is present in block , starrc asking for .lef file of that submacro (frame.lef) , why?
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    Why def file is needed apart from gds file for starrcxt?

    Why def file is using along with gds file during spef generation using starrc?
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    Inductance and parasitic extraction?

    Finally I got the answer, Inductance will come into picture when width of the interconnect is more or frequency is high. Z=R+Lw (Impedance of the interconnect/net). R= resistance L= inductance w= frequency scenario 1 ) when frequency is more inductance part dominates. scenario 2 ) when width...
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    Inductance and parasitic extraction?

    inductance of the metal layers in the layout is not included in parasitic extraction....Why not considering ? even the chip is working at high frequency?
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    Help Me << Galaxy common Galaxy ICC not enabled>>

    Hi Friends, I installed Synopsys ICC in 'Linux Mint 15 cinnamon' version (Not Debian version). Used SCL 10.9.3 and ICC E-2010.12 (AMD 64 & Common.tar files). . my lmgrd report is below 22:15:46 (lmgrd) ----------------------------------------------- 22:15:46 (lmgrd) Please Note: 22:15:46...
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    The error message about "unmaped cell" when dft_insert

    Add dw_foundation.sldb library during synthesis.
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    Why should we place hard macros manually in PnR?

    for the macro placement first do the flyline analysis, that is analyze the connections between modelnpins and macro and macro to the combo logic, and macro to macro. this will give you the idea about the placement of macro with optimal routing resources (So we are doing all the steps manually).
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