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Recent content by gsheng

  1. G

    How to make a 5M resistor on chip?

    The long channel mos shows different resistor value under different bias conditions. Its value is signal dependant.
  2. G

    How to make a 5M resistor on chip?

    But this need accurate clock.
  3. G

    Why use N+ diffusion resistor as ESD protection?

    poly resistor and diffusion resistor in esd But diffusion resistor has parasitic diode. It will influnce the ESD performance.
  4. G

    How to make a 5M resistor on chip?

    The resistor's parasitic cap need not very small because the signal is very large. I also want cap divider.
  5. G

    How to get rid of schematic annotation in Cadence schematic?

    Re: How to get rid of schematic annotation in Cadence schema You can select the menu: Results->Annotate->Design Defaults
  6. G

    How to make a 5M resistor on chip?

    Because I want to ac coupling a high speed signal, the cap must be small(around tens fF). Just a trade off between common mode settling time and input signal speed.
  7. G

    How to make a 5M resistor on chip?

    I want to use such a large resistor for ac coupling common mode clamp. Any idea is welcome. Thanks.
  8. G

    How to designer a good current multiplier in CMOS?

    Some ways may work. For examples, MOS in subthreshold region, parastic pnp device. But the performance is not good. Any good suggestion? Thanks.
  9. G

    DAC simulation testbench

    dac simulation I'm now designing a current DAC. Beacuse it's the first time I design this kind of circuit, I don't know what kind of simulation i need. Is there any intact testbench for DAC simulation? Thank you.
  10. G

    How to determine the Kvco value of a VCO?

    I'm designing.
  11. G

    How to determine the Kvco value of a VCO?

    Pratically Kvco curve is not so linear near the operating frequency. How to determine the Kvco value of a VCO?
  12. G

    a question about a design of comparator!

    OR you can use one comparator at different times
  13. G

    what's the disadvantage of this CMFB circuit?

    When Vo+ or Vo- swing too high, differential pair enters large signal region,ie ,one branch cut off, the other flows total tail current.
  14. G

    floating well PAD ESD problem?

    Do you mean path(2) is available? I do want to know why?
  15. G

    how to design analog low pass filter for vlsi design

    Re: how to design low pass filter for vlsi design Maybe other selections, such as digital filter? sc filter?
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