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Recent content by gs65

  1. G

    How does a read and write control work in SRAM

    Hi, In the diagram that you have attached ,there is no read circuitary. to read the data from sram , we use sense amplifiers (differential amplifier). bit lines will be given as input to sense amp. the output of sense amp will be your dout
  2. G

    [SOLVED] related to cadence spectre

    Hi, Is there any option to run hspice netlist from spectre?, if so how to do that?
  3. G

    HSPICE Mosfet model level

    hi, Higher the level, features are more and hence accuracy.
  4. G

    [Moved]: Differences between Single stage and Two stage operational amplifiers

    Re: Differences between Single stage and Two stage operational amplifiers The output from a single stage amplifier is usually insufficient to drive an output device.In other words, the gain of a single amplifier is inadequate for practical purposes. Consequently, additional amplification over...
  5. G

    Please help me to write a VERILOG code for MODULO 14 counter

    hi, go through below link . they have explained for mod 8 counter. Referring that prepare for mod 14, if you get any doubt, you can message ,i will help...
  6. G

    [moved] Project help in verilog - convert matlab code

    hi, yes, you can convert .
  7. G

    What is reverse antenna effect

    hi, go through this link...
  8. G

    Channel length modulation parameter? (Lambda kappa Pclm)

    Re: channel length modulation parameter? (lambda kappa Pclm) hi, all the three defines the channel length modulation (clm) . The parameter that defines clm depends on the device models of SPICE that you are using. 1st generation models - clm is defined by lambda 2nd generation - kappa 3rd...
  9. G

    HSPICE D Flip Flop hold rise (it rises and fall back!)

    hi, i guess some problem with your code, send the code of d flipflop. the code which you have attached does not contain line related to d flipflop
  10. G

    [SOLVED] inverter width and length

    hi, 2:1 ratio is done ,in order to make sure that rise and fall time of the output are same. if we increase the width values , the driving strength of the inverter (current) increases .
  11. G

    8bit Adder troubles simulating

    can you tell me what error you are getting
  12. G

    what is difference between Structural, behavior and test bench in VHDL

    i have done it using verilog. i think it is possible with vhdl also
  13. G

    what is difference between Structural, behavior and test bench in VHDL

    test bench is defining the stimuli for your code. where as structural and behavioral are different types of modelling your code
  14. G

    capacitor impedance question ???

    @eng_ahmed_osoma: impedance refers to the resistive property of the capacitor. at low frequencies it is very high and for high frequencies it is low.by using this property only we are defining rc filters
  15. G

    [SOLVED] Partial products in radix-2 modified booth algorithm

    i am not getting how you got those partial products.can you upload the document that you refered
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