Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Just to tell one more thing exp pulses kicked ass when it came to jitter I could easily have 47ps jitter without SNR degradation. I've implemented sine pulses too and they gave also good very results.
For those who wonder which topology was best, it was the hybrid one for a 3rd order single bit...
Yeah I know I've read those papers too but sometimes you have to come up with something new :pp ...
In papers they equal DT loop gain and CT loop gain and use residues theorem or modified z transform to calculate the "optimal" coeffs. They get their DT coeffs using Schreier matlab toolbox and...
I have the script in maple and also one in matlab to calculate those coefficients from DT to CT but only for FB and FF. Plus I want 3D graphs , you know, SNR,coeff1,coeff2,coeff3...Going to CT from DT you get "optimal" integrator coeffs but what about SNR? If DT to CT gives me (0.2,0.5,0.8) and...
sigma delta modulator dt-to-ct
I've implemented CT SD in matlab, not using simulink cause I wanna see exactly what's happening when you "play" with parameters.
Simulation is really pain in the ass especially when you want to calculate the integrator coefficients !! It takes a looooooooooot of...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
