Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Green_Ic

  1. G

    voltage controlled oscilators

    Hi all.One question.In VCO regarding stage numbers,with increasing stage number,we decrease the output frequency,but what becomes a good with increasing stage number? Because I saw,that mostly we don't put the stage numbers in minimum. It connects with to drive the output load or maybe PSRR or SNR ?
  2. G

    Shielding in IC analog layout design

    Hi.Could you please say to me,what can be the differences,when we are shielding the signal net with VDD or VSS in IC layout design.For example the analog signal from clock.
  3. G

    Differential amplifier with active load

    Hi, How will change(increase or decrease) the gain(Av) of diff pair,if the W of M4 transistor is increase?
  4. G

    Operational Transconductance Amplifier

    Hi, Could you please tell, for what used ota diff pair load diode connected transistors and latch?
  5. G

    Input common mode diff pair

    Hi, I run the simulation on diff pair positive input connected with negative input and I want to find input common mode diff pair. I run .dc analisys... .dc vin 0 vdd 0.001 Could you say please how I can find input common mode in this simulation?
  6. G

    Two stage operational amplifier

    Hi, I want to design two stage op amp with n-mos input diff pair and I have one question,why the second stage of op amp is p-mos input common source and what can be if the socond stage is n-mos input common source? Thanks.
  7. G

    Diff pair power supply rejection ratio

    Yes it's a PSRR test setup
  8. G

    Diff pair power supply rejection ratio

    I run the ac analysis,put ac=1 in VDD and connect the positive output with negative input to make a negative feedback(for compensation power noise) and diff amp worked in follower mode... And DC psrr values are different,but in first scheme,when is go the first pole the psrr is increase,but with...
  9. G

    Diff pair power supply rejection ratio

    Hi, I run the PSRR simulation for current source load diff amp and active current source load diff amp.And the PSRR plots are different and this diferences are conditioned by the diode connection. Please tell how I can explain this plots. Attached picture... Thanks.
See more

Part and Inventory Search

Back
Top