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Hello sir , can you tell me how to find worst case delay of combinational logic or critical path delay of combinational logic in encounter RTL compiler. can you tell what commands to be used?????
Thank you sir it helped me..
I have one more question ,, when i give command synthesize -to_generic it gives a warning combinational loop has been found and its been disabled.. is this error in the design??? Can you tell how to rectify it???
Sir can you please tell how to hand map these inverters???
by which commands to hand map those inverters???
and also how to use preserve command???
my delay cell module name is dealy3e, inside it there are instantiations of inverters i1,i2,i3,i4,i5,i6.,, the inverter module name is inv, can you...
i am designing an asynchronous processor , so i need delay cells , so i used 6 back to back inverters. :-)
i will try what you said and get back to you. :-)
i want to synthesize a design consisting of 6 cascaded inverters , when i type the command synthesize -to mapped its eliminating all inverters . please tell me how to avoid this problem. all i want is 6 cascaded inverters synthesized....:-P
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