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Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization
can we use transimission gate in a standard cell design ?
and what are the advantages on nand gate based logic ?
the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate...
AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates
suggest me or guid me regading this is the circuit correct ?
I read the UG ,thank for the information,i finally found the flow to follow on my project which is characterizing a standard cell "asynchronous latch"
1.schematic ----->tool CDesigner SE
2.layout ----->tool CDesigner LE
4.RC extraction Star RC...
I am a VLSI student doing my masters in VLSI & Embedded sys. As a final year student i need to do a project. im searching for internships couldn't find any (operchunity)openings. so i am looking to do my own project.
My idea was to design a EDA tool for FSM (finite state machines). i.e when i...