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Recent content by gong.kidd

  1. G

    Booth algorithm hardware implementation

    Re: booths algorithm hardware thanks for ur document, it's bit help to me
  2. G

    how to get singals on low level module when mix simu

    Hi, guys Can anyone tell me how to get singals on low level modules when using Verilog and VHDL simulaiton. my structure as below: Testbench: Verilog Top file : VHDL modules I want to get signals: Verilog. It will be error when I use "." like all verilog files, and how...
  3. G

    How to halt simulation process automatically in VHDL

    Yes, I used it in my RTL, it works in NCsim, not in Modelsim
  4. G

    How to halt simulation process automatically in VHDL

    how to halt a process Hi guys, can anyone there is the VHDL statements which have the function like system task $stop in Verilog? Thanks
  5. G

    Help me write a test bench for full adder and 4:1 mux?

    test bench 1. U can generate the test vecor from C(ramdom) or some else verification software. 2. use $readmemh. 3. comparing vector from input files with data output from adder.
  6. G

    What's the best VHDL/Verilog/SystemVerilog editor?

    linux verilog coding editor why not UltraEditor?
  7. G

    [DC] Determine parameter in set_input_delay?

    If u synthesize modules which is nothing without outer environment, that use 40% clock period; if else, should refer datasheet of outer chip.
  8. G

    synopsys design compiler

    U can add some parameter when simulating on simulation software such as NC
  9. G

    Why do we need DC if we can only use PT for synthesis?

    prime time and dc difference DC is a widely used synthesis tool for ASIC, and it can do some simple timing analysis; PT is a very effective STA tool.
  10. G

    What is the most popular simulator for HDL?

    Modelsim, I think VCS and NC dont have Windows version
  11. G

    H.264 Decoder IP core

    I dont think there are the free IP in Internet. It's too new.
  12. G

    this VIOLATION?????????

    Maybe, there are synchronous DFF in ur design, and remove the "set drive 0 [input rst_n]". BTW, Because the reset signal is not controlled by clock edge, u can ignore this violation.
  13. G

    gatelevel simulation error

    That's warning ,not Error. The module has one more port which is not be connected
  14. G

    Only generics of type INTEGER are supported for synthesis

    Re: Only generics of type INTEGER are supported for synthesi Just replace this(boolean style value) with an integer, and using the relative operation where use "ResetRegFile ".
  15. G

    How can I do power consumption estimation with VCD file?

    prime power report_power Thanks any question,can u tell me what is the db file in the script? DB file for DC synthesis or for physical design? thanks again
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