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Recent content by gnomix

  1. gnomix

    Interfacing DDR2 micron component to virtex5 Bank

    Try this link: https://www.xilinx.com/support/documentation/boards_and_kits/ug199.pdf
  2. gnomix

    [clock] 26.6Mhz from 80Mhz.

    try this code :) Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk26M is port( clk,reset : in std_logic; outclk : out std_logic); end clk26M; architecture p1 of clk26M is signal count : std_logic_vector(1 downto 0); signal ck1,ck1_dly : std_logic; begin...
  3. gnomix

    3.3V, 2.5V and 1.2V power supply generation for Spartan 3

    Re: 3.3V, 2.5V and 1.2V If you like a plug-and-play solution see: **broken link removed** only one resistor to generate any value from 0.76 to 3.6 v starting from 3v to 5V input
  4. gnomix

    Help to find an alternative to sharp LH79524

    Hi, I'm seeking an alternative to the sharp LH79524 32bit Arm SoC, with the following integrated main feature: · 10/100 BaseT Ethernet MAC · USB 2.0 or 1.0 · Color LCD Controller min 800x600 · Serial Interfaces like: - UARTs - IrDA Can someone help me? Regards Gnomix
  5. gnomix

    Information about Xilinx ISE 6.3 !

    Re: X1L1NX ISE 6.3 is out it is fantastic, yesterday he has been released the 6.3 and today it is available the service pack !!!https://direct.xilinx.com/direct/swhelp/series6/6í_sp1/6_3_01i_pc.exe. Shame!!!!!!
  6. gnomix

    JTAG programming of EPCS config memories

    see the following link at page 24: https://www.altera.com/literature/hb/cfg/cyc_c51013.pdf
  7. gnomix

    how to use 2 "clk" in one "process"!! ??

    Re: how to use 2 "clk" in one "process"! >but, does these code produce the condition that >"if (vref'event and vref= '1' and rts0= '1') or (reset = '1') "?? The difference is that in my source the"(vref'event and vref= '1' and rts0= '1')" reset is syncronous with the CLK2. see the attached...
  8. gnomix

    how to use 2 "clk" in one "process"!! ??

    Re: how to use 2 "clk" in one "process"! You can use only a single clock (CLK2) and re-sample the "vfef" to generate a synchronous reset. See the following example .... signal sync_reset : std_logic; signal vref_sh : std_logic_vector(2 downto 0); .... .... .... begin -- generate a one CLK2...
  9. gnomix

    effect of sensitivity list on the hardware generated in vhdl

    Re: effect of sensitivity list on the hardware generated in Theoretically, if you omitting the "b" signal in the sensitivity list, the result is a Latch instead of a Xor. but attention, not all synthesis tools work at the same way. Therefore the result not e' sure!
  10. gnomix

    What is better for FPGA manufacturer, Xilinx or Altera?

    Re: Xilinx or @ltera? Ok, Both vendors satisfy your requirement but, for my experience, I think that an other requirement must be held in consideration. The local F.A.E. support. Many times the difference is given does not give the tools or from the devices but from the support of the supplier...
  11. gnomix

    QuartusIIv3 Vs. QuartusIIv4

    Hi, I have the following question about quartus: Using the same source (and the same constrain) I found different timing performance using the qII.3 and QII.4. In particular the compilation with the new version is worse respect the old version (about 10%). Has someone found the same problem or...
  12. gnomix

    How to implement a divider by VHDL?

    divider vhdl Try this one.
  13. gnomix

    is there any tool that could translate verilog into vhdl?

    Re: is there any tool that could translate verilog into vhdl You can use X-HDL 3.2 It is the premier Verilog <=> VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, "hand tweaks" of the translated code...
  14. gnomix

    problem with ISE6.1 synthesizer

    It is very hard answer to your question without know the source code. if it isn't a problem please share the source code so we can analyze it.
  15. gnomix

    Req. synopsys models of AMS RAM

    Hi, I'm seeking the synopsys models of AMS Single Port RAM in 0.35µm CMOS Process (CSD) possibly in the following size: A) 32x16 B) 256x16 C) 4kx16. I need of these to perform a preliminary size/timing analisys of my chip. Has someone these models? Regards Gnomix

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