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Recent content by Gizmotoy

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    Strange simulator behavior for code in Verilog

    TrickyDicky is definitely correct. I tried swapping the "x++;" assignments for "x <= x + 1;" equivalents. Once completed, simulator performed exactly as intended. It's interesting that Altera's synthesis tool didn't seem as bothered by it as ModelSim, but am happy to have found the cause. I...
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    Strange simulator behavior for code in Verilog

    Seriously good eye on the extra clock in the counter. It seemed like the least of my problems so I had left it in for the time being. I've got it fixed up now, though. I do kind of think the simulator might be lying to me. I spent a few hours tonight in SignalTap, and the behavior seemed to...
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    Strange simulator behavior for code in Verilog

    I've been using VHDL for awhile now, and am relatively new to Verilog. I feel like I'm probably making an obvious mistake, but I'm not having much luck finding it. I'm working on creating a serial interface to a motor controller that uses an 8N1 serial protocol. I'm targeting an Altera...
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    VHDL to Verilog Conversion Issue - Blocking vs. Non-blocking?

    It was actually a completely different section of code, and I swapped it out pretty fast so I thought I was good. Lesson learned. I did narrow down the problem. always @(posedge CLOCK) begin if (CLEAR == 1'b1) begin data_z <= 1'b0; data_2z <= 1'b0; enable_z <=...
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    VHDL to Verilog Conversion Issue - Blocking vs. Non-blocking?

    Thanks for the reply. For those that are now confused, I changed the first post, apparently as FvM was replying. I eventually came to the same conclusion, and by just some luck happened upon what the actual issue was, which is what is now in the first post. Sorry for switching things around...
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    VHDL to Verilog Conversion Issue - Blocking vs. Non-blocking?

    VHDL to Verilog Conversion Issue - Blocking vs. Non-blocking and Register Delays? Hello. I have a good amount of experience in VHDL, but I'm trying to learn Verilog. I thought it might be worthwhile to hand-convert some of my VHDL designs into Verilog in order to learn the language. I have...
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    [SOLVED] Verilog 2001 and Ports with widths based upon parameters?

    Thank you! That worked perfectly. I was hoping there was a way to do this with the newer syntax. Thanks again.
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    [SOLVED] Verilog 2001 and Ports with widths based upon parameters?

    I'm new to Verilog, but have a bunch of experience in VHDL. I'm trying to replicate something I accomplish with Generics in VHDL, but I'm having a bit of trouble. I understand that you could define port widths in pre-2001 Verilog using something like: module adder (a,b,c); parameter WIDTH = 2...
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