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Hi all,
I am having some problems with DDR timing constraints.
So far I have:
create_clock -name virt_clock -period 6
create_clock I_DQS_90 -period 6
create_clock I_SYS_CLOCK -period 6
set_input_delay .7 -max -clock [get_clock virt_clock] -add_delay
set_input_delay .7 -max -clock...
Wandola,
There is a special file that you can create called the cds2gds map file. The gds layer list should be defined by your vendor. CDS stands for cadence design systems format, which typically uses a different mapping scheme than the technology vendor uses. By creating this cds2gds file you...
There are many issues with clock domain crossing.
In asynchronous designs you need to be worried about setup/hold time violations as well as metastability.
If you are switching between two clocks (i.e. two clocks muxed or clock gating) you need to be worried about glitches in the clock.
If...
Typically you would use the set_input_transition on a pin that you are unsure of the source. This is a great way to constrain maximum transition time at a top level pin
(i.e. at the pad). set_driving_cell works best when used in conjunction with -lib_cell option. This allows synthesis to...
When the temperature of a semiconductor rises, electrons in the valence band gain enough thermal energy to jump to the conduction band. This leaves what we call a "hole" in the valence band, it is more or less a simplified way of naming an empty state in the valence band.
When an electric...
Thank You,
I am glad to see that your problem was resolved. Just remember to always be cautious when using the unofficial std_logic_arith/std_logic_unsigned/std_logic_signed libraries. Remember that numeric_std is the ONLY official IEEE library for arithmetic operations, and it was designed do...
library ieee;
use ieee.std_logic_1164.all
use ieee.numeric_std.all
signal cnt_req : unsigned(1 downto 0)
process (clk_i)
begin
if(clk_i'event and clk_i = '1') then
if rst_i = '1' then
cnt_req <= (others => '0');
else
if ctrl_in_er_en_o_temp = '1' and ctrl_in_sent_i = '1'...
Hello All,
I am currently working on designing a DDR Interface from the ground up (no IP available, didn't want to go with Synopsys IP). The trouble I am having is defining clock groups.
I would like to set a clock that starts at the pin of my received strobe circuitry, this goes through some...
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